Highlights

  • dorsaVi shares rose 2.50% to AUD 0.041 on 18 June 2026, following the release of latest operational update.
  • The company finalised the design package for its first integrated RRAM-CMOS validation chip.
  • The chip was developed with NTU Singapore and ITRI Taiwan.
  • The program now moves toward tape-out and staged silicon implementation.
  • Key features include write-and-verify circuitry, Compute-in-Memory capability and standard commercial CMOS integration.

dorsaVi Limited (ASX:DVL) shares advanced 2.50% to AUD 0.041 during the morning session on 18 June 2026 after the company announced that it had finalised the design package for its first integrated RRAM-CMOS validation chip. The stock remains up 105.00% over the past year, with the latest update drawing attention as the program now moves from final design into tape-out and staged silicon implementation.

The update appears favourable as the company has completed an important design stage and is preparing the chip for fabrication. According to dorsaVi, the validation chip is intended to test three core capabilities for its ultra-edge intelligence roadmap: more reliable RRAM programming, Compute-in-Memory operation and integration using standard commercial CMOS front-end wafers.

Company Overview

dorsaVi is an ASX-listed company focused on ultra-edge intelligence and wearable sensor technology. Its platform is designed to support real-time, AI-driven decisions locally at the point of sensing, without relying on cloud connectivity.

The company’s wearable sensor technology captures and assesses human movement and position outside a biomechanics laboratory in real-time conditions. dorsaVi’s solutions are used across clinical applications, elite sports, and occupational health and safety. The company is also building hardware foundations for ultra-edge computing through investments in neuromorphic computing and RRAM memory technology.

Its focus areas include ultra-edge intelligence, workplace applications and clinical solutions. In workplace settings, dorsaVi supports employers in assessing injury risk and testing changes to occupational health and safety design, equipment and methods. In clinical markets, its ViMove+ technology provides objective assessment, monitoring outside clinics and immediate biofeedback.

RRAM-CMOS Design Completion Moves Program Forward

The company announced that the full design package for its first integrated RRAM-CMOS validation chip has been completed. The chip has been developed in collaboration with NTU Singapore and ITRI Taiwan and is now ready to move toward fabrication.

This milestone shifts the program from design completion into tape-out and staged silicon implementation. For semiconductor development, this step is relevant because it moves the project closer to producing physical silicon that can be tested and validated.

dorsaVi said the results from this validation chip are expected to inform its subsequent 22-nanometre implementation pathway. The company is using this stage to gather practical silicon-level data before progressing further toward commercial-scale development.

Write-and-Verify Feature Targets Memory Reliability

One of the central features of the validation chip is its self-checking write-and-verify circuitry. RRAM stores data through resistance states rather than through charge storage. In real array operation, the final resistance state after a write operation may vary due to device-to-device variation, cycle-to-cycle variation, array parasitics and operating conditions.

This variability can create marginal programmed states, particularly if a memory cell sits too close to the sensing threshold. In such cases, read circuits may have reduced margin when distinguishing between stored “1” and “0” states.

To address this, dorsaVi has included write-and-verify control in the validation chip. After a write operation, the circuit reads back the programmed RRAM state and checks whether it falls within the intended resistance window. If the state is marginal or outside the target range, the circuit can support further tuning or identify the condition for optimisation.

The company said this converts RRAM programming from an open-loop write event into a more controlled process. The feature is designed to improve programming accuracy, reduce marginal memory states, increase sensing margin and provide data for future reliability and yield optimisation.

Compute-in-Memory Adds Edge AI Capability

Another key element of the chip is Compute-in-Memory functionality. In conventional chip architectures, data is often moved repeatedly between memory and a separate processor. dorsaVi noted that this movement can be a major contributor to power consumption and latency, particularly in edge devices operating under tight energy and response-time limits.

The company’s Compute-in-Memory design aims to reduce repeated data movement by allowing selected compute operations to occur closer to where data is stored. The same RRAM array can store programmed resistance states and also operate as a local compute structure.

The design supports two operating modes. In Binary Memory Mode, the array stores and retrieves digital data in a conventional way. In Compute-in-Memory Mode, programmed resistance states are used as compute weights, supporting accumulation across up to 64 inputs locally before producing a compact digital compute output through the CIM readout path.

This feature is intended to validate how future RRAM-based hardware could support lower energy use and faster local decision-making in ultra-edge applications.

Commercial CMOS Pathway Supports Scalability

dorsaVi also highlighted the chip’s integration pathway. The RRAM component is designed to sit in the chip’s back-end-of-line metal layers, above the standard CMOS front-end transistor circuitry.

This means the validation chip can use commercial CMOS front-end wafers sourced through TSMC, followed by partner-led back-end-of-line and RRAM integration. The company said this approach avoids the need to alter the underlying CMOS transistor layer.

The integration pathway provides a commercial CMOS foundation, a BEOL-compatible route for adding RRAM, future density scaling potential and practical data for process optimisation, manufacturability assessment and node migration.

Target Markets Include Exoskeletons, Robotics and Industrial AI

dorsaVi said the validation chip is aimed at high-value markets where devices need local, low-power, non-volatile intelligence. These include exoskeletons, defence, robotics, industrial AI and intelligent sensing.

For smart exoskeletons, the company pointed to smart EMG sensor nodes that read muscle signals to determine user intent, such as swing, push-off or fatigue. These systems require fast writes within the control loop and non-volatile storage for each user’s baseline.

In robotics, particularly industrial and humanoid robotics, joint controllers may need to run position and torque loops while holding calibration data. Non-volatile memory can support systems that retain calibration across power cycles.

For on-device industrial AI, dorsaVi noted that locally running models require weights to be held close to compute. Compute-in-Memory and BEOL density may allow models to sit on-die and operate without power-heavy reloads.

Next Steps After Design Completion

With the design package finalised, dorsaVi said the program is progressing on three fronts.

First, the chip will proceed to tape-out as scheduled. Second, validated silicon will move toward integration into dorsaVi’s sensing platform, with the objective of embedding intelligence directly into wearable sensor hardware. Third, the company plans to engage prospective partners and customers across target markets including exoskeletons, defence, robotics and industrial AI.

Group Chief Executive Officer Mathew Regan said finalising the design of the first RRAM-CMOS validation chip marks an important milestone for the program. He added that the step confirms the architecture is manufacturable under standard commercial foundry conditions and clears the path to physical silicon required for performance validation.

What This Means for Investors?

dorsaVi’s latest update indicates that its RRAM-CMOS validation chip program has moved past the design stage and is advancing toward fabrication. The announcement brings together several investor-relevant elements, including completed chip design, collaboration with NTU Singapore and ITRI Taiwan, planned tape-out, standard commercial CMOS integration and future validation for ultra-edge applications. The share price gain suggests investors responded positively to the company reaching this development milestone, while upcoming silicon validation remains an important next step for the program.