Key Highlights

  • Nanoveu’s Wholly Owned Subsidiary EMASS has received the first engineering samples of its 16nm ECS-DoT system-on-chip from TSMC.
  • The 16nm program has progressed from GDS sign-off and tape-out to packaged silicon.
  • The new chip adds integrated Bluetooth Low Energy, expanded SRAM, finer power management, an object-detection accelerator and a hardware floating-point unit.
  • Bring-up, benchmarking and characterisation are now scheduled to measure power, performance and functional behaviour.

Nanoveu (ASX:NVU) has moved its next-generation edge AI semiconductor program into a new stage after receiving the first engineering samples of its 16nm ECS-DoT system-on-chip. The silicon was fabricated by Taiwan Semiconductor Manufacturing Company for Nanoveu’s wholly owned semiconductor subsidiary, EMASS. The design was signed off in December 2025 and taped out in January 2026 before moving through wafer fabrication, packaging and delivery. The company said this is the first ECS-DoT device produced on an advanced FinFET process.

16nm Program Moves from Design to Physical Silicon

The latest milestone means the ECS-DoT design is now available as packaged engineering silicon rather than remaining at the architecture or physical-design stage. Before delivery, EMASS completed front-end design, synthesis and physical design before final GDS sign-off in December 2025. Tape-out followed in January 2026, when mask data was sent to TSMC and fabrication began. The wafers were subsequently processed, diced and assembled into packaged engineering samples.

The image on page 2 of the announcement shows the packaged 16nm engineering sample alongside a close-up of the silicon die. The company also provides the physical layout of the chip, illustrating the shift from the design stage to manufactured hardware.

16nm Device Expands the ECS-DoT Product Family

EMASS now has ECS-DoT silicon at two semiconductor process nodes. The existing 22nm ECS-DoT is the commercial product currently in customer evaluation and design-in across applications including wearables, industrial sensing, asset tracking and smart infrastructure. The 16nm version is intended to provide greater on-chip integration while using the same programming model, software stack and toolchain as the 22nm product.

According to Nanoveu, customers can begin development using the 22nm version and later move applications to the 16nm device with limited changes to application code. This common platform approach allows EMASS to support both semiconductor generations from the same software and engineering base.

New Features Increase On-Chip Integration

The 16nm ECS-DoT retains the RISC-V core, dual deep-learning accelerators, scalable compute-to-memory interconnect and always-on architecture used in the 22nm generation. The newer chip adds an integrated Bluetooth Low Energy subsystem covering the analog front end, RF transceiver and associated signal-chain components. In some applications, this could remove the need for a separate wireless chip.

The chip also includes expanded on-chip SRAM to support larger neural networks and vision or multi-sensor workloads. A fine-grained power-management fabric provides power gating, dynamic clock gating and autonomous low-power states, while a dedicated object-detection module is designed for lightweight vision workloads. The non-maximum suppression stage of this accelerator is covered by US Patent No. 12,651,452 B2, which is exclusively licensed to EMASS.

For the first time in the ECS-DoT family, the 16nm device also contains a hardware floating-point unit supporting FP16 and FP32 operations. Nanoveu said this is intended to support digital signal processing, mixed-precision AI workloads and easier porting of existing floating-point code and libraries.

Benchmarking Will Determine Measured Performance

The next stage is bring-up, during which engineers will power the device, establish communication and confirm that core functions operate as designed. EMASS then plans to move into benchmarking and characterisation across functional behaviour, RF performance, AI throughput, latency, memory behaviour and power consumption.

The company intends to measure active, idle and deep-sleep power, wake-up latency and energy per inference using representative vision, audio and sensor-fusion workloads. The results will be compared with the 22nm device and pre-silicon estimates. Nanoveu plans to publish a summary of measured power and performance once characterisation is complete, after which engineering samples and evaluation boards are expected to be offered to selected customers and partners.

Key Insights

Nanoveu has completed the fabrication stage of its 16nm ECS-DoT program and now has physical engineering samples available for testing. The new device increases on-chip integration through additional memory, wireless connectivity, AI acceleration and floating-point capability. The next phase will focus on validating whether the manufactured silicon performs as designed, with measured power and performance data expected after the characterisation program.