Highlights

  • dorsaVi has commenced the tape-out process for its first resistive random-access memory and complementary metal-oxide semiconductor validation chip.
  • The milestone moves the program from a completed design package into staged physical silicon implementation.
  • The validation chip is intended to generate electrical and process data covering memory operation, write-and-verify behaviour and Compute-in-Memory functionality.
  • dorsaVi is targeting future applications across artificial intelligence, robotics, electric vehicles, defence, exoskeletons, wearables and industrial hardware.

dorsaVi Limited (ASX:DVL) has commenced the tape-out pathway for its first resistive random-access memory and complementary metal-oxide semiconductor validation chip, moving its 22-nanometre development program from finalised design into physical silicon implementation. The latest milestone is intended to provide the practical testing data required to assess the company’s memory architecture under commercial semiconductor manufacturing conditions.

Shares of dorsaVi rose 15.38% to AUD 0.030 during the afternoon session on 15 July 2026 following the release of the development update. The stock remains up 50.00% over the past year, with the latest market movement coinciding with the company’s transition from chip design work into the manufacturing and validation stage of its resistive random-access memory program.

About dorsaVi

dorsaVi is an ASX-listed technology company focused on intelligence at the ultra-edge, where artificial intelligence-driven decisions are processed locally at the point of sensing rather than relying entirely on cloud connectivity.

The company’s existing technology includes wearable sensor systems used to capture, quantify and evaluate human movement and body position outside laboratory environments. Its platforms can collect information in real time and in everyday conditions for periods of up to 24 hours.

dorsaVi’s technology has applications across clinical care, workplace safety, occupational health and elite sport. The company is also investing in the hardware foundation required to support local artificial intelligence processing through neuromorphic computing and resistive random-access memory technology.

Its broader development strategy is directed towards enabling devices to store information, process data and make decisions locally while reducing dependence on remote computing infrastructure.

Tape-Out Moves Chip Beyond Completed Design

Tape-out is the stage at which a completed integrated circuit design package is prepared for physical manufacturing.

For dorsaVi, the process marks the transition from engineering and design finalisation into the staged production flow needed to create physical silicon for testing. The company recently completed the design of the validation chip and has now started implementing that design with tier-one semiconductor partners.

The tape-out milestone does not represent the completion of the final commercial product. Instead, it begins the manufacturing pathway through which the chip architecture can be tested under physical conditions.

The resulting silicon is expected to allow dorsaVi and its partners to evaluate how the memory array, control circuits, sensing components, write-and-verify functionality and Compute-in-Memory structures operate together.

This data will be used to guide future development work, including circuit optimisation, process refinement and progression towards later 22-nanometre resistive random-access memory and complementary metal-oxide semiconductor implementations.

Commercial Foundry Process Forms Manufacturing Base

The validation chip will follow a staged implementation pathway built around commercial complementary metal-oxide semiconductor front-end wafers sourced through Taiwan Semiconductor Manufacturing Company.

Following production of the front-end wafers, dorsaVi’s partners are expected to undertake back-end-of-line processing and integrate the resistive random-access memory layers.

The completed wafers will then progress to wafer-level electrical testing.

This manufacturing approach allows the company to test its technology on a commercial semiconductor foundation rather than relying on a completely separate or customised manufacturing system.

According to dorsaVi, integrating the memory stack into established back-end-of-line processes provides flexibility for process development, electrical testing and future migration to other manufacturing nodes.

The company’s stated objective is to develop an architecture that can be incorporated into standard commercial complementary metal-oxide semiconductor production flows.

Validation Chip to Generate Practical Silicon Data

The validation chip is designed to collect physical silicon data across several technical areas.

These include resistive random-access memory and complementary metal-oxide semiconductor integration, memory-array operation, resistance-state separation, sensing margins, write-and-verify behaviour and wafer-level testing methods.

The chip will also be used to examine Compute-in-Memory functionality, which allows certain calculations to occur within or close to the memory array.

The information produced during testing is expected to show how the different components behave when integrated into one physical device.

This stage is intended to move the development program beyond simulations and design models by providing measured electrical and process information from manufactured silicon.

The results may then be used to refine the memory platform, improve circuit design, adjust manufacturing processes and prepare the architecture for later development stages.

Memory and Processing Combined in One Architecture

Conventional computing systems generally separate memory and processing functions.

Information is stored in memory and repeatedly transferred to a processor when calculations need to be completed. This movement of data can contribute to power consumption and processing delays.

The issue can become more significant in edge devices that operate with limited energy, restricted connectivity or strict response-time requirements.

dorsaVi’s architecture is designed to integrate resistive random-access memory directly with complementary metal-oxide semiconductor circuitry and Compute-in-Memory structures.

Under this model, the memory array can store data while also carrying out selected calculations locally.

The validation chip will enable the company to test whether its memory arrays and Compute-in-Memory features operate together under physical silicon conditions.

Testing is also expected to assess readout behaviour, sensing pathways and the ability to distinguish between different resistance states within the memory cells.

Write-and-Verify Functionality Enters Physical Testing

A further area of focus is the chip’s dedicated write-and-verify circuitry.

Resistive random-access memory stores information by changing the resistance state of a memory cell. The write-and-verify process is intended to confirm whether a cell has reached the required state after data has been written.

The validation chip will allow the company to evaluate this behaviour in manufactured silicon rather than solely through digital models or pre-fabrication design work.

The results are expected to help dorsaVi understand how the memory array, write circuits, verification functions and sensing pathways interact.

This process information may support adjustments to operating conditions, circuit parameters and memory programming methods.

The validation stage will also provide information required to develop repeatable wafer-level testing procedures for future chips.

Technology Targets Rising Edge-AI Requirements

dorsaVi is positioning its resistive random-access memory platform for applications where artificial intelligence functions need to operate locally.

Edge artificial intelligence systems process information on or near the device generating the data. This can reduce the need to send information to a remote cloud platform before receiving a response.

Local processing may be relevant for devices that require rapid decisions, operate with limited connectivity or must manage power consumption carefully.

The company’s architecture is aimed at combining non-volatile memory with low-power local processing.

Non-volatile memory retains stored information when power is removed, making it potentially relevant to battery-powered, autonomous and intermittently connected systems.

dorsaVi stated that its development roadmap is focused on supporting on-device intelligence across sensing and hardware platforms.

Two Potential Commercial Pathways Identified

The company has outlined two possible pathways through which its resistive random-access memory technology could address artificial intelligence memory requirements.

The first is direct integration into end devices.

Under this model, the memory architecture could be embedded into hardware used in areas such as robotics, electric vehicles, wearable systems, exoskeletons, medical devices or industrial platforms.

The second pathway involves working with semiconductor foundries and fabless chip developers to create specialised chips for defined applications.

dorsaVi stated that both approaches are intended to use established manufacturing infrastructure rather than requiring the construction of new semiconductor facilities.

The company believes compatibility with commercial complementary metal-oxide semiconductor processes may support adoption across different hardware platforms.

However, the current program remains focused on validation and testing, and the announcement did not provide a commercial production date or revenue forecast for the technology.

Robotics and Exoskeleton Applications Form Part of Roadmap

Robotics and exoskeleton systems are among the target markets identified by the company.

These platforms may require memory and processing systems that can make decisions locally while operating within power and latency constraints.

For example, robotic hardware may need to interpret sensor information and respond without waiting for a remote computing system.

Similarly, powered exoskeletons may require local processing to assess movement, balance or user inputs in real time.

dorsaVi’s existing experience in wearable sensors and movement measurement provides a connection between its current platforms and the longer-term ultra-edge hardware strategy.

The resistive random-access memory program is intended to provide part of the semiconductor foundation required for local intelligence within such systems.

Defence and Industrial AI Markets Also Targeted

The company has also identified defence and industrial artificial intelligence hardware as potential markets.

Defence systems may operate in environments where secure local processing, low power use and limited connectivity are important considerations.

Industrial equipment may similarly require rapid on-device decisions in locations where continuous cloud access is unavailable or undesirable.

The company’s memory architecture is being developed with the aim of supporting local data retention and computation.

However, deployment into these sectors will depend on successful silicon validation, further development, application-specific engineering and progression towards scalable manufacturing.

The current tape-out program is designed to generate the technical information needed to inform those later stages.

Electric Vehicles and Wearables Expand Addressable Uses

Electric vehicles represent another potential application for local, low-power processing and non-volatile memory.

Modern vehicles can contain multiple sensing and control systems that require rapid access to stored information and real-time processing.

dorsaVi has also highlighted wearable and medical devices, where energy use, physical size and local processing capability can influence product performance.

Wearable systems may benefit from the ability to collect, store and analyse data without transmitting every measurement to an external platform.

The company’s existing ViMove+ clinical technology already focuses on remote movement assessment, out-of-clinic monitoring and immediate biofeedback.

The resistive random-access memory program represents a separate but related effort to develop underlying hardware capable of supporting future locally intelligent devices.

Workplace and Clinical Businesses Remain Part of Company

Alongside its semiconductor development activities, dorsaVi continues to operate technology platforms across workplace and clinical applications.

Its workplace products are used to assess employee movement and injury risk and to evaluate proposed changes to workplace design, equipment and operating methods.

The company has previously worked with corporations and organisations including London Underground, Vinci Construction, Crown Resorts, Caterpillar, Boeing, Monash Health, Coles, Woolworths, Toll, Toyota, Orora, Mineral Resources and BHP.

Within the clinical market, the ViMove+ platform is used to provide objective assessment, monitoring and immediate feedback.

The company identifies physical therapy, hospital-in-the-home services and elite sport as key areas within its clinical activities.

Its ultra-edge intelligence strategy extends this focus by seeking to enable more processing to occur locally within devices and sensor systems.

Validation Data to Shape Future 22-nm Development

The current validation chip forms part of a broader 22-nanometre development pathway.

The company intends to use the electrical and process data generated from the chip to guide future architecture and manufacturing decisions.

Areas to be assessed include the integration of the memory macro with peripheral circuits, the performance of memory arrays, the effectiveness of write-and-verify functions and the behaviour of Compute-in-Memory structures.

Testing will also provide information on sensing margins, resistance states and wafer-level evaluation techniques.

The findings may identify areas where design modifications or process adjustments are required before moving towards later 22-nanometre implementations.

dorsaVi described the current milestone as an execution step that advances the program from a completed design package into physical silicon production and validation.

Management Focuses on Testing and Commercial Scaling

Group Chief Executive Officer Mathew Regan said the start of tape-out confirmed that the resistive random-access memory architecture had reached a point where it could enter standard commercial foundry conditions.

He added that the resulting silicon would provide the information required to test performance and refine the technology.

The company’s immediate focus is on executing the next testing stage and using the findings to advance the program towards potential commercial scaling.

The announcement did not provide a timetable for completion of fabrication, the release of test results or the commencement of commercial production.

As a result, the next stages will depend on manufacturing progress, integration work and the outcome of electrical validation.

What This Means for Investors

dorsaVi’s latest update marks the movement of its resistive random-access memory program from completed chip design into the physical manufacturing process.

The tape-out milestone is operationally favourable because it allows the company to begin generating real silicon data rather than relying only on design-level analysis.

The validation chip will test the interaction between the memory array, complementary metal-oxide semiconductor circuitry, write-and-verify functions, sensing pathways and Compute-in-Memory structures.

The use of commercial front-end wafers and established back-end-of-line manufacturing processes is also intended to assess whether the architecture can be integrated through existing semiconductor infrastructure.

Nevertheless, the program remains at the validation stage. The company must still complete fabrication, integration, wafer-level electrical testing and technology refinement before progressing towards broader commercial deployment.

Investors are likely to monitor the completion of silicon manufacturing, the outcome of electrical testing, performance of the Compute-in-Memory features and further progress towards the planned 22-nanometre development pathway.